Spacer width is a useful parameter for controlling parasitic source/drain resistance in transistors. Transistor operation is typically optimized with a spacer width that moves source/drain junctions closer to the channel without over-running source/drain extensions. In conventional semiconductor processes, however, a single spacer width is used for all transistor devices in a circuit. This width is usually dictated by the subset of transistor devices that have the highest impact on product constraints. However, independent control of spacer widths for different transistor groups is desirable because it enables more extensive optimization of each group, thereby resulting in a greater overall device performance.
There is thus a need in the art for a method for making transistors and other semiconductor devices which permits the independent optimization of spacer widths for two or more transistor groups. These and other needs may be met by the devices and methodologies described herein.